1. Field of the Invention
The present invention relates generally to methods for manufacturing three-dimensional (3D) multi-component electronic structures that consists of simple active and passive integrated circuit elements. More particularly, the present invention relates to fabricating a plurality of simple three dimensional electronic component packages such as a DC-DC converter in form panels where each package includes at least an active semiconductor die and a passive, two-terminal, electrical circuit component (capacitor inductor and/or resistor).
2. Description of the Prior Art
Three-dimensional (3D) integrated circuit fabrication techniques in the semiconductor industry where active semiconductor dies and passive electrical circuit elements are vertically stacked and interconnected to form high density integrated circuit modules have evolved to satisfy the demand for space-constrained, digital electronic devices such as smart phones, tablet computers, laptop computers and the like. Techniques for fabricating such high density 3D integrated circuit modules, variously referred to as Chip-Scale-Packages (CSPs), Multi-Chip-Modules (MCMs), Systems-in-a-Package (SIPs) and Wafer-Level-Chip-Scale-Packages (WLCSPs), all essentially require a combination of or the equivalent of:                a carrier or substrate support surface;        an adhesive film covering the support surface of the carrier;        a layer of discreet contact pad arrays of electrically conductive material placed on the adhesive surface for a plurality of particular integrated circuit modules;        an initial layer of discrete semiconductor dies and passive electrical components each having terminals registering with, and metallurgically and electrically connecting to particular contact pads in each discreet array of contact pads for each particular integrated circuit module;        a temporary layer of a resist material covering the initial layer of arrays of discrete semiconductor and passive electrical components and vacant contact pads in each particular circuit module;        via passages or openings penetrating through the temporary layer of resist material exposing the vacant contact pads, and exposing chosen terminals of the initial array of discrete semiconductor dies and passive electrical components;        an electrically conductive pillar constructed in each via passage, and an electrically conductive bump placed on each exposed terminal of the semiconductor dies and passive electrical components, respectively metallurgically and electrically connecting to the exposed contact pads and to the exposed terminals;        removal of the temporary layer of resist material exposing the initial array of contact pads, discrete semiconductor dies and passive electrical components with constructed electrically conductive pillars and bumps in each particular integrated circuit module;        at least a second layer of discrete semiconductor dies and passive electrical components having terminals that register with and metallurgically and electrically connecting to the conductive constructed pillars extending up from the contact pads and to the conductive bumps extending up from the exposed terminals in each particular integrated circuit module;        encapsulating the initial and second layers above the adhesive film covering the carrier substrate surface in a layer of electrically insulating, permanent wafer bonding material creating a layered structure containing a plurality of the particular integrated circuit modules;        removal of a top layer of the electrically insulating, permanent wafer bonding material from the created structure for reducing the thickness of the layered structure;        removal of the carrier substrate support surface, and the covering adhesive film exposing bottom faces of the conductive pad array on a bottom face of the created structure;        an interconnect face (or lead frame) structure consisting of patterns electrically conductive material selectively interconnecting between the exposed bottom faces of the conductive pads in each particular integrated circuit module, and a layer of permanent electrically insulating material selectively covering the electrically conductive interconnect pattern of each particular integrated circuit module;        an array of conductive bumps connecting metallurgically and electrically to exposed sections of the conductive interconnect pattern of each particular integrated circuit module; and        singulation of the discreet integrated circuit modules formed in the created structure.        (See generally U.S. Pat. No. 8,288,201, Pagaila et al. entitled “SEMICONDUCTOR DEVICE AND METHOD OF FORMING FO-WLCSP WITH DISCRETE SEMICONDUCTOR COMPONENTS MOUNTED UNDER AND OVER SEMICONDUCTOR DIE” & U.S. Pat. No. 8,222,716, J. A. Bayan, entitled “MULTIPLE LEAD FRAME PACKAGE”.)        
While a myriad of different types of small inductors, resistors and capacitors can and have been incorporated into such integrated circuit modules, there are limitations. Existing package level integration techniques incorporating such components involve either costly manufacturing processes, high tooling costs, or both. Also, in applications where load currents are in excess of 100 mA and switching waveforms have rise- and fall times in the few nanoseconds (ns) range as in the case of advanced electronic DC-DC converters, the drawbacks are electronic noise (EMI & RFI), complexity, and expense.
DC-DC converters are essential both in space-constrained digital devices powered by rechargeable batteries such as smart phones, tablet computers, laptop computers, and in larger digital systems that have multiple subsystems, e.g. desk top computers, where the different subsystems require power at different voltages.
There are different topologies of DC-DC converters, the most common being a step-down or ‘Buck’ topology where output voltage less is than the input voltage, a step-up or ‘Boost’ topology where the output voltage is greater than the input voltage and a “single-ended primary-inductor” converter (SEPIC) or ‘Buck-Boost’ topology where output voltage can be greater or less that the input voltage.
For space-constrained digital devices powered by internal, rechargeable batteries or solar cells, DC-DC converters offer a very small and efficient method of producing a precisely controlled voltage output. In particular, the voltage output of battery power sources decreases across a range as charge depletes, and increases across that range when connected with an external direct current recharging power source. A DC-DC converter receives the energy from such variable DC power outputs, stores that energy in either in the magnetic field of an inductor component and/or an electrical field of a capacitor component, and then outputs that energy at either a higher or a lower output voltage levels as required by the particular integrated circuit module with which it is interconnected whether digital or analog.
In larger digital systems, each IC subsystem may require energy at a particular voltage to properly function. In this case the DC-DC converter receives DC energy input from voltage output of a power supply for the system and outputs that energy at an optimum voltage for the proper function of the module it is serving.
In short, there is a high demand for small, reliable DC-DC converters and similar simple electronic circuit packages that include at least an active semiconductor die controller and a passive, two-terminal, electrical circuit component in the electronic industry. They are essential to, but cannot be effectively or practically incorporated into more complex integrated circuitry modules. Also, current state-of-the art DC-DC converter packages and similar packages currently being interconnected with complex integrated circuitry modules are expensive, hard to interconnect, and ill-suited for mass production.
In particular, looking FIG. 1A illustrating an existing state-of-the-art lead frame package for a DC-DC converter 109 that includes an integrated circuit (IC) controller, 101, an inductor 102, and a capacitor, 103, arranged on top of an etched copper lead frame 104. The IC controller 101 is wire bonded to the lead frame 104. The passive, two-terminal circuit components (inductor 102 & capacitor 103) are soldered on the lead frame 104. The entire assembly is over-molded with a permanent, electrically insulating molding material 109 using conventional map-molding tools developed for the fabrication of QFN (Quad Flat No-lead) or DFN (Dual Flat No Lead) packages. Typically, in conventional QFN packages containing a single semiconductor die that dissipates significant amount of heat, the central portion of the lead frame is formed to have a large rectangular shape underneath the die, extending sideways, in order to facilitate heat transfer from the semiconductor die to the printed circuit board. The DC-DC converter module of FIG. 1A uses parts of the central portion of lead frame 104 to connect the terminals of passive components 102 and 103 to individual isolated segments of the etched lead frame. The disadvantages of such lead frame packaging relate to time and expense for creation of a copper lead frame interconnecting between the package components, and a fragmented exposed (and electrically conductive) bottom surface that complicates layout of underlying circuitry components, e.g., a printed circuit board (PCB). Fragmented lead frames also significantly reduce the removal rate of heat generated within the package. Also, the thickness of the molding material 109 electrically insulating and securing the inductive and capacitive components 102 & 103, and copper lead frame thickness (˜200 μm) increase package height to non-optimal levels in space constrained destination systems. Finally, such packaging technology requires complicated and expensive tooling in order to accomplish injection over-molding of such structures for mass production.
FIG. 1B illustrates another state-of-the-art integrated DC-DC converter module, including a wafer-level chip scale package (WLCSP) integrated circuit controller (a semiconductor die) 105 having solder-bump terminals, placed, exposed, on top of an inductor 102. The inductor surface is patterned with edge plates 106 for interconnection. The main drawback of this approach is that it requires custom inductor designs, and a complex manufacturing flow, hence very expensive. The minimum achievable package height is also greater than 1 mm. Other drawbacks include fragility of the exposed semiconductor die 105 that is both thin and brittle and can be damaged by chipping and cracking when placed on an underlying printed circuit board (PCB) by pick-and-place machines prior to solder re-flow. High thermal resistance and light sensitivity are also potential concerns.
FIG. 1C illustrates a state-of-the-art package-level integrated DC-DC converter module, where die-embedding PCB substrate technology is used to encase the integrated circuit controller 101 and interconnection traces between the controller and an inductor 102 in an embedding PCB substrate laminate 107. This approach uses solder balls 108 to connect the die-embedded package to an underlying PCB a particular DC-DC converter module is attached to by the end-user. This type of module integrates an IC, inductor and two capacitors 103 into a single module. Drawbacks include a need to use die-embedded PCB substrate technology requiring copper electroplating that limit production to relatively small panels, hence significantly increase manufacturing costs.
FIG. 1D illustrates still another state-of-the-art package-level integrated DC-DC converter module, wherein die-embedding PCB substrate technology is used to encase an integrated circuit controller in an embedding PCB substrate laminate 107. Copper interconnection paths between the controller and an inductor are electroplated within the laminate. The die embedded PCB substrate laminate is then over-molded with electrically insulating material 109, encapsulating the passive circuit components. This approach uses a Land Grid Array (LGA) footprint to connect the die-embedded package subsystem to a PCB of a particular device. Major drawbacks of this approach are manufacturing cost relating to copper electroplating, small panels for mass-production, and injection molding tooling for over-molding the package. Also, the combination of laminate and over-molding the inductive components significantly increases the height of the package.
Finally, FIG. 1E illustrates a state-of-the-art package-level integrated DC-DC converter module, wherein an industry standard Dual Flat No-lead (DFN) packaged IC controller 110, is attached to an inductor 102 by means of an adhesive. The inductor 102 is specially designed with a channel-like cavity underneath, the DFN package. The inductor terminals 111 (at opposing ends of the inductor) are formed by edge plating. The inductor terminals 111 and the DFN device terminals 112 are co-planar, and are solder-connected to a conventional PCB by the end user. The electrical connection between the IC controller 110 and the inductor 102 are formed by copper interconnect traces on the PCB. The main drawbacks of this approach relate to customization of the inductor structure to provide edge plated inductor terminals 111 and a “channel” for receiving the IC controller 110. Also, fabrication of the DFN structures is expensive, time consuming, involve lead frames, wire bonding and over-molding with permanent electrically insulating molding materials.